The present invention relates in general to data processing systems, and in particular, to bus interfaces in data processing systems.
As system clock speeds have increased in data processing systems, reflecting an increase in the speed of central processing units, the speed of transfers on buses in the system has had to increase correspondingly. The transfer of data across a bus connecting elements of the data processing system is necessarily limited by the physical separation of the elements. One method which has been developed to transfer data across a bus is wave-pipelining in which a data signal is launched on the bus before the previous data has been captured into a receiving device across the bus. In other words, data is pipelined across the bus interface between elements in a data processing system in essentially an xe2x80x9cassembly linexe2x80x9d fashion. Once the xe2x80x9cpipelinexe2x80x9d or xe2x80x9cassembly linexe2x80x9d is filled, data is delivered at an average rate that exceeds the latency across the interface.
In a typical data processing system, data may be transferred from a source device to a plurality of receiving devices. Different receiving devices will be coupled to the source, or sending, device across bus interfaces having differing electrical lengths, and therefore differing latencies.
Additionally, in a single device receiving a plurality of data signals, each signals may have a different latency. Variations may arise from manufacturing tolerances, design limitations, for example variations in line lengths, and time dependent effects, such as data dependent jitter (inter-symbol interference), clock jitter, and noise.
Moreover, data is expected to be delivered synchronously. That is, data is expected to be delivered on a predetermined cycle of the system clock. If data is delivered earlier or later than expected, errors may occur.
In a wave-pipelined interface, timing analysis is made more complicated because both the fast path and slow path are equally important. The data valid region, that is the time interval during which data can be reliably sampled, is reduced as the difference in time between the fast path and the slow path coupling the source, or sending, device to one or more receiving devices increases. If the difference in time between the fast path and the slow path becomes as large as the period of the bus clock, synchrony will be lost. Moreover, skew in the sampling clock may further reduce the data valid region. As bus interface speeds increase, smaller timing variations between the fast and slow paths are required, and clock skew constraints become more severe. However, the control of clock skew and timing variations may be limited by physical constraints presented by the layout of the data processing system. Therefore, there is a need in the art for methods and apparatus to deskew the data at the receiving device end of the interface, and increase the time during which data can be reliably sampled.
The aforementioned needs are addressed by the present invention. Accordingly, there is provided, in a first form, a wave-pipelined interface apparatus. The apparatus includes a plurality of delay devices, each device being operable for receiving a corresponding data signal, each delay device having a preselectable delay time, and outputting the data signal after the preselected delay time. Circuitry coupled to the plurality of delay devices is operable for setting each the preselectable delay time, each the preselected delay time being set in response to an arrival time associated with each the data signal.
There is also provided, in a second form, a method of dynamic wave-pipelining in a interface which includes the step of setting an arriving edge of each data signal of a plurality of data signals to correspond to an arriving edge of a latest arriving data signal in the plurality of data signals.
Additionally there is provided, in a third form, a data processing system including a dynamic wave-pipelined interface. The data processing system contains a central processing unit (CPU), and a receiving device coupled to the CPU operable for receiving at least one data signal from the CPU. The receiving device has a data receive unit including a plurality of delay devices, each device being operable for receiving a corresponding data signal, and having a preselectable delay time. Each delay device outputs the data signal after the preselected delay time. The data processing system also contains circuitry coupled to the plurality of delay devices operable for setting each the preselectable delay time, each preselected delay time being set in response to an arrival time associated with each data signal.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.